1. Technical Field
This invention generally relates to layout versus schematic (LVS) verification error locating. More particularly, this invention relates to an efficient method for locating short circuits of shorted circuit paths in circuit layouts.
2. Description of Background
Generally, a successful Design rule check (DRC) ensures that a circuit layout conforms to the rules designed/required based on user specific manufacturing techniques. However, DRCs do not verify that any particular circuit layout coincides with a particular circuit design. Layout versus schematic (LVS) verification does however perform comparisons between a desired circuit design (e.g., nodes and connections) and a desired circuit layout (e.g., NFET layers, metal layers, vias, etc).
In some circumstances, a LVS check returns one or more “short circuit” errors. It is appreciated that a simple error does not pin-point a location of a short circuit. Furthermore, it is exceedingly difficult to locate a short circuit in a circuit layout, particularly as a layout design becomes large (e.g., in an ALU design or any other large circuit layout).